1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor field effect transistor (CMOSFET) and, more particularly, to a CMOSFET suitable for simplifying its process and improving the reliability of dual gate lines, and method of to fabricating the same.
2. Discussion of the Related Art
Development and research has been directed to reducing a size of a MOSFET constituting integrated circuits in order to obtain good performance of circuits and its high integration. As a result, semiconductor integration circuits have been scaled down to smaller than micron sizes. A width of a gate line in a MOSFET has been narrower, and a parasite capacitance between gate lines is substantially increased due to the increase of wiring voltages and the reduction of a gap between the gate lines caused by the micronization of gate lines, so that the rate of circuits for transmitting signals is considerably reduced. That is, since a delay time which has an influence on the rate of circuits for transmitting signals is indicated by RC which a resistance R of a gate line by a parasite capacitance C between gate lines makes, the resistance R of a gate line is required to be decreased in order to improve a rate of circuits for transmitting signals.
In a method for decreasing a line resistance of a gate electrode, a polycide structure in which silicide is deposited on polysilicon for forming a gate electrode is used instead of a structure in which only polysilicon is used for forming a gate electrode.
As integration of CMOSFETs has been higher, unit devices become smaller in size. An LDD structure is applied to a MOSFET in order to solve the problem of hot carrier which is caused by the short channel effect due to the decrease of the size of unit devices. A gate electrode for a PMOSFET is doped with n-type impurity ions which are identical ones doped into a gate electrode in an N-type MOSFET, such that current doesn't travel between source and drain, but in a bulk inside a substrate. Accordingly, in order to solve the problem of a resulting low punch through breakdown voltage between source and drain, p-type impurity ions are doped into a gate electrode. A CMOSFET produced in this manner is named a dual gate CMOSFET.
In a dual gate CMOSFET, a rate of transmitting signals is decreased as its integration is increased. Accordingly, a structure of a gate using polycide is desired. On account of structural characteristic that silicide is formed on polysilicon so as to form a polycide gate, impurity ions doped into the polysilicon are diffused into the silicide formed on the polysilicon in a process at a high temperature and the impurity ions contained in the silicide are easily diffused. At this time, because of silicide which is known to be diffused more easily than polysilicon, dopants move in the boundary between an n-type gate and a p-type gate, thereby making a threshold voltage of the MOSFET unstable. In order to solve this problem, a method has appeared in which a diffusion-preventing layer is formed at the interface of the silicide and the polysilicon. In the method, a structure of a gate electrode is a silicide structure composed of 3 layers which are silicide/TiN/polysilicon layers.
A conventional CMOSFET using a dual gate will be described below with reference to the accompanying drawings.
FIGS. 1a to 1n are cross-sectional views showing process steps of a conventional method of fabricating a CMOSFET.
Referring initially to FIG. 1a, on an n-type semiconductor substrate 1, there are formed a p-type well 2, an n-type well 3, and a field oxide layer 4.
Subsequently, on the entire surface, there are successively formed a gate oxide layer 5 and an undoped polysilicon layer 6, as shown in FIG. 1b.
Thereafter, a photo resist film PR.sub.1 is coated on the entire surface of the polysilicon layer 6 and then patterned by an exposure and development process so that the polysilicon layer 6 is partially exposed, as shown in FIG. 1c. Next, using the photo resist pattern PR.sub.1 as a mask, an ion implanting process is performed to turn the undoped polysilicon layer 6 over the p-type well 2 into an n-type polysilicon layer 6a. In this case, phosphorous ions are used.
Then, the remaining photo resist film PR.sub.1 is removed as shown in FIG. 1d. Subsequently, another photo resist film PR, is coated on the entire surface of the polysilicon layer 6 including the n-type polysilicon layer 6a and then patterned by an exposure and development process until the polysilicon layer 6 over the n-type well 3 is partially exposed. Using the photo resist pattern PR.sub.2 as a mask, an ion-implanting process is performed to turn the undoped polysilicon layer 6 over the n-type well 3 into a p-type polysilicon layer 6b. In this case, boron (B) ions are implanted.
Next, as shown in FIG. 1e, the remaining photo resist film PR.sub.2 is removed. Then, a TiN layer 7, which functions as a diffusion preventing layer, and a WSi.sub.2 layer 8, which is a first silicide layer, are successively formed on the entire surface of the n-type and p-type polysilicon layers 6a and 6b.
Subsequently, a photo resist film PR.sub.3, as shown in FIG. 1f, is coated on the WSi.sub.2 layer 8 and then patterned by an exposure and development process so that placements of gate electrodes are defined.
Thereafter, as shown in FIG. 1g, using the photo resist pattern PR.sub.3 as a mask, the WSi.sub.2 layer 8, the TiN layer 7, and the n-type and p-type polysilicon layers 6a and 6b are selectively removed by an etching process, thus forming a first gate electrode 9 composed of the n-type polysilicon layer 6a, the TiN layer 7, and the WSi.sub.2 layer 8 over the p-type well 2, and a second gate electrode 10 composed of the p-type polysilicon layer 6b, the TiN layer 7, and the WSi.sub.2 layer 8 over the n-type well 3.
Next, the remaining photo resist film PR.sub.3 is removed as shown in FIG. 1h. Still another photo resist film PR.sub.4 is coated on the entire surface of the semiconductor substrate 1 including the first and second gate electrodes 9 and 10 and then is patterned by an exposure and development process so that the region of the n-type well 3 is masked. Thereafter, using the first gate electrode 9 over the p-type well 2 as a mask, phosphorous ions are implanted into the p-type well 2 at both sides of the first gate electrode 9.
Subsequently, as shown in FIG. 1i, the remaining photo resist film PR.sub.4 is removed. Next, yet another photo resist film PR.sub.5 is coated on the entire surface of the semiconductor substrate 1 including the first and second gate electrodes 9 and 10 and then patterned by an exposure and development process so that the region of the p-type well 2 is masked. Using the second gate electrode 10 over the n-type well 3 as a mask, boron ions are implanted into the n-type well 3 at both sides of the second gate electrode 10.
As shown in FIG. 1j, the remaining photo resist film PR.sub.5 is removed. Impurity ions implanted into the p-type and n-type wells 2 and 3 are activated to form n-type lightly doped impurity diffusion regions 11 under the surface of the p-type well 2 at both sides of the first gate electrode 9 and p-type lightly doped impurity diffusion regions 12 under the surface of the n-type well 3 at both sides of the second gate electrode 10. That is to say, lightly doped drain (LDD) regions are formed under the surface of each of the wells 2 and 3 at both sides of each of the gate electrodes 9 and 10. Thereafter, an oxide layer is deposited on the entire surface of the substrate including the first and second gate electrodes 9 and 10 and then is etched-back to form sidewall spacers 13 on both sides of each of the first and second gate electrodes 9 and 10.
Next, as shown in FIG. 1k, another photo resist film PR.sub.6 is coated on the entire surface of the semiconductor substrate 1 including the first and second gate electrodes 9 and 10 and then patterned by an exposure and development process so that the n-type well 3 is masked. Subsequently, using the first gate electrode 9 and its sidewall spacers 13 as masks, an arsenic (As) ion implanting process is executed to the exposed p-type well 2.
As shown in FIG. 1l, the remaining photo resist film PR.sub.6 is removed. Then, still another photo resist film PR.sub.7 is coated on the entire surface of the semiconductor substrate 1 including the first and second gate electrodes 9 and 10 and then patterned by an exposure and development process so that the region of the p-type well 2 is masked. Next, using the second gate electrode 10 and its sidewall spacers 13 as masks, BF.sub.2 ions are implanted into the exposed n-type well 3.
Subsequently, the remaining photo resist film PH.sub.7 is removed as shown in FIG. 1m. The As ions and the BF.sub.2 ions doped into the p-type and n-type wells 2 and 3, respectively, are activated to form n-type heavily doped impurity diffusion regions 14 under the surface of the p-type well 2 at both sides of the first gate electrode 9 and its sidewall spacers 13, and p-type heavily doped impurity diffusion regions 15 under the surface of the n-type well 3 at both sides of the second gate electrode 10 and its sidewall spacers 13. That is to say, heavily doped source/drain regions are formed. Thereafter, a titanium (Ti) layer 16 is formed on the entire surface of the substrate including the first and second gate electrodes 9 and 10 and their sidewall spacers 13 for performing a silicide process.
Then, as shown in FIG. 1n, the semiconductor substrate 1 is annealed to form a TiSi.sub.2 layer 17, which is a second silicide layer, at the interface of the heavily doped impurity diffusion regions 14 and 15 and the Ti layer 16. Next, the Ti layer 16 that has not been reacted is removed.
The conventional method of fabricating a CMOSFET using a dual gate has the following problems.
First, an ion implanting process should be performed to each of polysilicon layers which are used as n-type and p-type gate electrodes and additionally lots of masking processes using photo resist films should be performed. Accordingly, the overall fabricating process becomes complicated and its productivity is decreased.
Second, although impurity ions are implanted to a polysilicon layers in order to decrease a resistance of a gate electrode, a simple ion implanting process can not achieve uniform impurity diffusion concentration of the impurity ions over the polysilicon, and thus a resistance of the gate electrode may be increased. As a result, the performance of a transistor becomes inferior and thus the reliability of highly integrated devices is decreased.
Third, in order to form a silicide layer on gate electrodes and on source/drain regions, a WSi.sub.2 layer, a first silicide layer, is formed on the gate electrodes, and a TiSi.sub.2 layer, a second silicide layer, is formed on the source/drain regions. That is, two processes should be performed to form the silicide layer, whereby the productivity is decreased.